A continuing demand exists for higher performance integrated circuits (“IC”), such as very large scale integrated circuits (“VLSI”). As a result, semiconductor manufacturers are challenged to increase the performance of transistors, such as n-channel field effect transistors (“NFETs”) or p-channel field effect transistors (“PFETs”), which are utilized in ICs.
One important measure of field effect transistor (“FET”) performance is speed, which is related to current in the FET. A typical FET includes a gate stack, which includes a gate electrode situated over a gate dielectric, a source and a drain, and a channel, which is situated between the source and the drain in a silicon substrate. The channel is also situated underneath the gate dielectric, which is situated over a substrate, such as a silicon substrate. When a voltage is applied to the gate electrode that is greater than a threshold voltage, a layer of mobile charge carriers, e.g. electrons in an NFET and holes in a PFET, is created in the channel. By applying a voltage to the drain of the FET, a current can be caused to flow between drain and source.
In the FET discussed above, the mobility of the carriers is directly related to the current that flows between the drain and the source, also referred to as FET current in the present application, which is directly related to the speed of the FET. Carrier mobility is a function of, among other things, temperature, electric field created between gate electrode and channel by the gate voltage, and dopant concentration. By increasing carrier mobility, FET current and, consequently, FET speed can be increased. Thus, as a result of increasing carrier mobility, FET performance can be desirably increased.
Thus, there is a need in the art for a FET having increased carrier mobility to achieve increased FET performance.